1. Field of the Invention
The present invention relates to clock data recovery (CDR).
2. Description of Related Art
The clock data recovery is a useful technique in digital data transmission that does not use a clock leased line. More specifically, a clock signal is superimposed on transferred data itself, and a receiving apparatus that has received the data reproduces the clock signal from the received data. Moreover, the receiving apparatus samples the data by using the reproduced clock signal. Such the clock data recovery is used in a high-speed communication interface, a display driver, an optical disk reproducing device and the like.
In the clock data recovery, a PLL (Phase Locked Loop) circuit is typically used. The PLL circuit includes a VCO (Voltage Controlled Oscillator) and can reproduce the clock signal by controlling a control voltage of the VCO such that a desired oscillation frequency is obtained. Such a state where a frequency and a phase of the reproduced clock signal are synchronized with respect to an input signal is called “lock” of the PLL circuit. However, in some cases, the PLL circuit does not operate normally due to various causes and thus the frequency of the reproduced clock is locked at a frequency different from the desired frequency. This state is called “false lock” of the PLL circuit. Since correct data reception is not ensured if the false lock occurs, it is important to detect the occurrence of the false lock at an early stage.
Japanese Patent Publication JP-2005-318014A discloses a method of detecting false lock. More specifically, a method of detecting false lock where a ratio between a data rate and a clock frequency is 1:n (where n is an integer equal to or larger than 2) is as follows. That is, data sampled based on the reproduced clock are monitored for a predetermined period, and occurrence probability of a pattern [0, 1, 0, . . . ] or a pattern [1, 0, 1, . . . ] of three or more bits during the predetermined period is calculated. If the occurrence probability is 0%, it is determined that the false lock of 1:n has occurred.